We are actively investigating the power of P4 language for specifying the packet processing operations:

  • Header parsing
  • Decision making (lookup tables, ACLs etc.) and the related actions (packet modifications)
  • Modified packet assembly (deparsing)

Our results show that it is possible to generate packet processing circuits beyond 100 Gbps for Virtex-7 FPGAs:

Screen Shot 2016-02-10 at 15.27.21Preliminary results of full P4 pipeline

Related publications

Header Parser Case Study

Adding TRILL protocol support into our HANIC and SDM firmware took two weeks in total, including roughly 1 day of manual modifications and verifications of header parser VHDL code. The modification of same-functions P4-generated header parser took around 15 minutes of writing P4 code only.