Network Development Kit

Easy to use framework for HW acceleration.

We provide the Network Development Kit (NDK), which allows users to quickly and easily develop new network appliances based on FPGA acceleration cards. The NDK is optimized for high throughput and scalable to support 10, 100 and 400 Gigabit Ethernet.

Key features:

  • Network module based on standard Ethernet Hard IPs with support 10 GbE, 100 GbE, 400 GbE and other speeds.
  • Ultra fast DMA module with 400 Gbps throughput based on PCIe Gen5 x16 interface.
  • Easy to use memory interface for single read/write data from/to card.
  • Automatic scripts for complete design synthesis. Single make command to create complete FPGA bitstream.
  • Linux kernel driver, DPDK support, user space library, tools for the configuration of components.
  • Easy creation of custom application by user-friendly API for component access and DMA transfers.

User Application

NDK is designed for creating new network applications with fast packet processing in a deep pipeline. The application core is a user logic which can benefit from NDK to capture packets from network interfaces and send any data to the host CPU using ultra fast DMA transfers. Receiving and sending network packets is handled by a network module (part of NDK). The packets are then transmitted to the application core via the data stream bus (compatible with AXI4-Stream/Avalon-ST). The same data bus is then used to transfer data to the host CPU. The entire NDK is designed to be scalable from tens to hundreds Gbps. It is ready to send and process more packets per clock cycle. The standard data buses are optimized to transfer more packets at once and thus further scale the throughput. We have designed the concept of MFB (Multi-Frame Bus) and MVB (Multi-Value Bus) to scale standard buses over 100 Gbps throughput. In terms of throughput, almost the only limitation is the available resources of the FPGA.

Many networking applications need large data structures or buffers. Therefore the NDK provides an easy to use interface for communication with external memories (typically DRAM). Users can utilize the interface for rapid development of a connection tracking table, flow cache or data buffers.

The user application implemented in the FPGA can be controlled by read/write requests to an assigned address range. These requests are transmitted from the SW to the application core via a CSR bus compatible with Avalon-MM. Read and write requests can be generated by the SW user application through a simple SW API.

Ultra Fast DMA transfers (DMA Medusa IP)

We provide a vendor-independent FPGA architecture and open-source Linux drivers for high-speed DMA transfers using the per-packet approach. The DMA is designed for  400 Gbps throughput and uses multi-channel architecture to support the distribution of data among CPU cores. The architecture is highly flexible and supports various high-end FPGA families and PCIe bus configurations (up to PCIe Gen5 x16). The DMA IP can utilize more PCI Endpoint blocks to scale throughput to 100, 200, and 400 Gbps.

We have already demonstrated the 400 Gb throughput of the DMA architecture on the Intel Stratix 10 DX Development Kit, but the same DMA engine can provide a very high throughput also for Xilinx UltraScale+ or Intel Agilex devices. The NDK Linux driver allows controlling all DMA channels separately. The NDK driver also provides a user-friendly API to connect your application core directly to the DMA IP. It is also possible to handle DMA transfers through the DPDK driver.

More information will come soon, stay tuned!