| Info | HW section | SW section | Addr space | Versions |
| Authors: | Tomas Martinek |
| Jan Korenek |
Monitoring of network traffic is a typical application with requirement of high performance. If 10Gps technology is assumed, up to 20 million packets arrive into the system per second. For each packet, it is need to analyze control information in header and provide packet classification. The classification process puts the packets into the specific catogories and it is based on reqirements of monitoring system. For some of categories, statistic information are produced and/or selected packets are sampled for detail analysis. The most critical part of monitoring adapter is payload checking, where the data of input packets need to be analyzed for containing the specific patterns.
We develope monitoring adapter intended for 10Gbps technology. The adapter provides input packet classification and supports three techniques of packet sampling (deterministic, probabilistic and byte deterministic). Further, it produces two kind of statistic information--statistic based on packet length and statistic based on timestamps. Finally, it allows the payload checking of specified packets for containing up to 120 patterns 16 bytes long.
SCAMPI design block structure.
The Scampi Common block (SCOM) is used for general design purposes. It contains identification register, which is important for software driver and global design detection. Further, the SCOM is used for design reset, IRQ enabling/disabling and input interface selection.
The TSU_COV design performs TSU_ADD handling by software. It makes available for software to request all three TSU modes (INIT, SHORT, FAST) and to read the actual time stamp value.
The Input Buffer (IBUF) is used as a storage for incoming packets. The packets are received from GMII interface and only those one with correct CRC are saved into the internal memory. Packets reading is performed via interface, which is very similar to FIFO one.
The Header Field Extractor is intended for analyzing of input packets. It is a processor based on RISC architecture controled by specific instruction set. HFE reads packets data from input buffer, analyses control information in its headers and produces specific data structures.
UH FIFO is memory organised as FIFO which contain Unified Headers (UH) generated by HFE processor. It has 16 items and is organised as circular buffer. LUP reads UH and performs classification. When UH processing is finished, it is released.
Packet FIFO is divided into two parts: PFIFO_A and PFIFO_B. Due to this PFIFO can provide inter-design connection. It converts 16 bit input data into 32 bit data. PFIFO_A is conected with four HFE interfaces and provides DRAM scheduler functions. It converts HFE data into new format PFIFO_B can work with and send them via four streams to PFIFO_B. PFIFO_B recieves 4 data strems from PFIFO_A, which are stored into FIFO16TO32. It is also connected with Sorting Unit (SU), Dispatcher (DISP) and SFIFO. It use SU records to sort packets from four streams into one in previous order (as they were recieved from HFEs). It also separates control data from input streams, sorts them and stores into SFIFO. DISP can read sorted 32 bit packets from PFIFO or it can free them directly without reading.
Look up processor (LUP) performs packet classification. LUP input is a structure called Unified Header which is created by Header field extractor and contain important informations from packet headers. Output is a record that controls packet processing in following blocks. LUP use TCAM and SSRAM memory. The Unified header classification starts in TCAM memory where part of Unified header is selected and matched. The TCAM result is address which points to the program stored in SSRAM memory. The program checks remaining part of unified header and is finished by EXE instruction which contain result (LUP) record.
Statistic Unit (STU) allows to create length and time statistic (number of packects, average packet length, minimal and maximal packet length, average interpacket time, etc.). Statistic unit contains 256 virtual statistic cores implemented as 256 sets of registers and only one processing unit. Set of registers which is used for statistic for actual packet is determined by LUP record.
Sampling unit (SAU) performs sampling of packets which are required to pass to the application. Sampling units contains 16 Sampling Cores (SC). Each Sampling Core can be configured to do deterministic, length deterministic and probabilistic sampling. The packet could be processed simultaneously in more than one SAU core. Sampling unit has two inputs: (1) LUP record created by Look up processor (LUP) and (2) length of actual packet. Output from SAU is 16bit sample vector. Each bit of sample vector corresponds to result of one Sampling Core.
Based on input control information, the Dispatcher component determines whether the packet from input FIFO component will be forwarded to the output, or discarded. Input control information is composed of two parts: (1) Sampling Record - specifies bit vector of Sampling Cores results; (2) Payload Checker Identifier - specifies the group of strings to be checked in packet payload. If none of Sampling Cores has sampled the packet and PCK Identifier is zero (no payload checking), then the input packet is discarded. Otherwise, the packet is forwarded to the output interface.
The Output Buffer is used as a storage for outgoing packets dedicated to software driver. The input packets arrive in format of "command protocol", which splits packet data from its control data. The Output Buffer decapsulates this protocol and stores packet and control data into the output memory separately at different memory positions. The control data are typically stored at beginning of memory buffer and packet data are stored from specified memory offset. The Output Buffer supports generic number of memory blocks and it also is responsible for interrupt (IRQ) generation, when packet arrive into the buffer.
