| Info | HW section | SW section | Addr space | Versions |
| Authors: | Jan Korenek |
| Jiri Tobola |
The goal of NIFIC project is development of 4-port Gigabit NIC card with HW filtration and HW packet forwarding. The input part is the same like in Liberouter project (IBUF, HFE, UH_FIFO, LUP), the output part is simplified to SW interface and direct packet transmitting components (without packet editing).
An incoming packet is received by the Input Packet Buffer and passed to the Header Field Extractor. The HFE pushes the body of the packet (including original headers) into the Packet FIFO (PFIFO). Meanwhile, it parses the packet's headers and creates a structure called Unified-header, which is stored in UH FIFO. Look up processor (LUP) performs lookup in the filtering and direct packet forwarding tables. The Lookup processor output (called LUP result) provide information about next packet processing.
The Dispatcher (DISP) binds together packet classification with packet body and executes the rule - packet is discarded, sent to SW (via SW_OBUF) or sent directly to output interface (via REP). Packets, which were sent to SW, are processed by operating system and then transmitted by the Output buffers. Packets, which were sent to replicator, are directly copied on one or more output interfaces.
NIFIC design block structure
Liberouter control component integrates ID component and some more features for design control like SW reset and IRQ handling.
The Input Buffer (IBUF) is used as a storage for incoming packets. The packets are received from GMII interface and only those one with correct CRC are saved into the internal memory. Packets reading is performed via interface, which is very similar to FIFO one.
The Header Field Extractor is intended for analyzing of input packets. It is a processor based on RISC architecture controled by specific instruction set. HFE reads packets data from input buffer, analyses control information in its headers and produces specific data structures.
UH FIFO is memory organised as FIFO which contain Unified Headers (UH) generated by HFE processor. It has 16 items and is organised as circular buffer. LUP reads UH and performs classification. When UH processing is finished, it is released.
Look up processor (LUP) performs packet classification. LUP input is a structure called Unified Header which is created by Header field extractor and contain important informations from packet headers. Output is a record that controls packet processing in following blocks. LUP use TCAM and SSRAM memory. The Unified header classification starts in TCAM memory where part of Unified header is selected and matched. The TCAM result is address which points to the program stored in SSRAM memory. The program checks remaining part of unified header and is finished by EXE instruction which contain result (LUP) record.
Packet FIFO is divided into two parts: PFIFO_A and PFIFO_B. Due to this PFIFO can provide inter-design connection. It converts 16 bit input data into 32 bit data. PFIFO_A is conected with four HFE interfaces and provides DRAM scheduler functions. It converts HFE data into new format PFIFO_B can work with and send them via four streams to PFIFO_B. PFIFO_B recieves 4 data strems from PFIFO_A, which are stored into FIFO16TO32. It is also connected with Sorting Unit (SU), Dispatcher (DISP) and SFIFO. It use SU records to sort packets from four streams into one in previous order (as they were recieved from HFEs). It also separates control data from input streams, sorts them and stores into SFIFO. DISP can read sorted 32 bit packets from PFIFO or it can free them directly without reading.
Dispatcher II is Dispatcher from Scampi design with some new features added by a cover. There are new FIFO for incoming processed packet headers and FSM, which can according to LUP classification forward packets to Replicator via IOS wires (combo6 - daughter card).
The Output Buffer is used as a storage for outgoing packets dedicated to software driver. The input packets arrive in format of "command protocol", which splits packet data from its control data. The Output Buffer decapsulates this protocol and stores packet and control data into the output memory separately at different memory positions. The control data are typically stored at beginning of memory buffer and packet data are stored from specified memory offset. The Output Buffer supports generic number of memory blocks and it also is responsible for interrupt (IRQ) generation, when packet arrive into the buffer.
The Replicator extracts protocol from the Dispatcher and transmits packets on one or more output interfaces. Throughput of direct packet forwarding is limited to 1.6Gbps (before replication) because of IOS connection.
The transmit buffer (TXBUFF) component provides an interface for SW driven packet transmit operation and a simple interface for HW controlled packet transmission. The packet output is done by the standard GMII interface.
