| Info | HW section | SW section | Addr space | Versions |
| Authors: | Jan Korenek |
| Jiri Tobola |
The main task of firmware in Liberouter project is to ensure fast packet routing and filtering IPv6/IPv4 using resources on COMBO6 card. The functionalities are concentrating to the several programmable gate arrays (FPGA), which handle packet reception from an input network interface, processing the header data, decision about the appropriate action and, finally sending it to the right interface.
An incoming packet is received by the Input Packet Buffer and passed to the Header Field Extractor. The HFE pushes the body of the packet (including original headers) into the dynamic memory. Meanwhile, it parses the packet's headers and creates a structure called Unified-header. The Unified-header is a fixed structure containing relevant information from packet headers. HFE also generates a structure that reflects the physical arrangement of headers in the packets. This structure is used by Output Packet Editor (OPE) for editing the packet before it is sent out of the router and is stored in DRAM together with the body of the packet.
Look up processor (LUP) performs lookup in the routing and firewalling tables. The Lookup processor output is a record that controls packet processing in following blocks. LUP uses Content Addressable memory (TCAM) and static memory (SSRAM). The Unified header processing starts in CAM memory. Part of Unified header is loaded into the memory and matched. The result is address pointed to program stored in SSRAM memory. It checks remaining part of unified header. The program is finished by EXE instruction containing LUP record. This record and packet identification is then send into the Replicator.
The REP block replicates the packet identification and pointers to the editing programs into the dedicated queues. REP computes the number of replicas of the packet that should be sent out and updates the number of pointers to this packet in DRAM scheduler. Then it copies the packet identification to desired output queues.
The Priority queues system stores the edit rules references generated by the Replicator along with the packet DRAM references. The packets are read by the Output packet editor, according to the assigned output interfaces and priority, processed, and sent to one of the output interfaces. Each of the Output packet editors reads the records from the PQ queue that has the highest priority and is not empty, processes the packet, and sends it out.
The OPE block modifies the headers of packets. The simplest modification of the packet is decrementing of the Next Hop Count in the IPv6 header (known as Time To Live in IPv4). More complicated operations include exchanging of two addresses in IPv6 headers width the Routing Header parameter.
Liberouter design block structure
Liberouter control component integrates ID component and some more features for design control like SW reset and IRQ handling.
The Input Buffer (IBUF) is used as a storage for incoming packets. The packets are received from GMII interface and only those one with correct CRC are saved into the internal memory. Packets reading is performed via interface, which is very similar to FIFO one.
The Header Field Extractor is intended for analyzing of input packets. It is a processor based on RISC architecture controled by specific instruction set. HFE reads packets data from input buffer, analyses control information in its headers and produces specific data structures.
UH FIFO is memory organised as FIFO which contain Unified Headers (UH) generated by HFE processor. It has 16 items and is organised as circular buffer. LUP reads UH and performs classification. When UH processing is finished, it is released.
Look up processor (LUP) performs packet classification. LUP input is a structure called Unified Header which is created by Header field extractor and contain important informations from packet headers. Output is a record that controls packet processing in following blocks. LUP use TCAM and SSRAM memory. The Unified header classification starts in TCAM memory where part of Unified header is selected and matched. The TCAM result is address which points to the program stored in SSRAM memory. The program checks remaining part of unified header and is finished by EXE instruction which contain result (LUP) record.
Replicator component is used for realization of multicast communication. It solves problem with sending packet to more output interfaces. Records from LUP (look up processor) and software are processed by Replicator. Each record contains structural information which determines list of output interfaces to which the packet is send and specifies how the record will be processed. Replicator processes this record, replicates packet reference and puts packet reference with information about next processing description to proper priority queue.
The Priority queues system stores the Replicator Records generated by the Replicator in dedicated queues. On request these Replicator Records are sent to the Output Packet Editors from the PQ queue that has the highest priority and is not empty. Records can be read also by software interface. This is useful in case the packet is better to be processed by software application. Special operation called 'write-back' is implemented to provide multicast feature. Priority Queues component implements modified FIFO Priority algorithm to avoid record starvation in lower-priority queues. The whole queues content is stored in external SSRAM memory (2MB).
The Output Packet Editor(OPE) is a stream processor doing the packet header editation and transmition via TX-buffers. The Liberouter design contains 4 OPEs (one for each interface). Those editations take in for example Hop Limit decrementation, Routing Options changes, Encapsulation/Decapsulation (for L3 layer), or Source/Destination Addresses changes (for L2 layer). It recieves Replicator Records from Priority Queues component which comprises of Packet Parameters and data pointer into DRAM memory and Edit Parameters pointer into SSRAM memory.
The OBUF component implements transmitting part of MAC layer described in standard IEEE 802.3. It receives packets from others components of the design (MAC clients) and stores them into the internal buffer of generic size. Further, the packets are transmitted through output interface. Input interface represents FrameLink protocol and output interface is the transmitting part of the GMII interface.
The Memory Scheduler unit stores packets and the Editing Parameters from the HFE units in the dynamic memory (DDR SDRAM), keeps reference counts for each packet (at its address in the memory), increments or decrements reference counts on Replicator or OPE demand, and reads a packet from the memory upon an OPE demand. Another important MSH function is to provide an equal access of the HFE and OPE units to the shared memory and shared address resources. The MSH should give fair amount of time to the requesting unit. Equal access should prevent starvation of units waiting for the address allocation (HFE), data read or a references counter decrement (OPE) etc. and congestion of units waiting for data store (HFE).
This component is interface for DDR SDRAM on Combo6X card. It consists of three parts. Lower part is responsible for memory initialization, proper timing and the whole data pipeline. Higher part decodes simple "Read" and "Write" commands to real SDRAM commands, i.e PRECHARGE, ACTIVE, READ and WRITE. SDRAM_LB_Conn connects localbus and any other unit to the rest of the driver.
