Author:

Jan Pazdera

COMBO PTM card design is a part of the whole TSU. It is dedicated to create and provide precise time stamp (3 modes) for add on card part. It must be initialized and adjusted by user drivers.

TSU - PTM part

Part of TSU placed on COMBO6 PTM card provides precise Time Stamps for another TSU part - TSU_ADD placed on Add on card. PTM design can be driven by software via PCI or via embeded Microcontroler MSP430F149IPM (vendor Texas Instruments). It can also communicate with external GPS unit which provides precise pulses every second. PTM design is based on four Time Engine Registers (TERs): INCR, RTR, TSR and PSR.

The VHDL design on COMBO-PTM card is divided into four parts: 1) TSU core 2) PCI interface 3) MCU interface 4) TSU_ADD interface to COMBO6+add on card

TSU core

TSU core consists of four 96bits-wide Time Engine Registers (TERs). The heart of the core is Real Time Register (RTR) which holds the actual time information. The INCremental Register (INCR) holds the value which is added every clk puls ( 60MHz) derived from internal precise Xtal. The ideal value of INCR should be close to 0x47 9531 9CA1 ( == 2^64 / 60M). The content of RTR is copied into Pulse per Second Register (PSR) on the leading edge of GPS signal (generated every second). For right setting of INCR register use two consecutive PSR values. Their difference should be as close 0x0000 0001 0000 0000 0000 0000 as possible. On demand from the COMBO6 + add on is RTR copied into Time Stamp Register (TSR) and send out to the COMBO6 + add on. Content of all registers can be read by PCI or MCU interface Only RTR and INCR can be modified by those interfaces. The width of all registers is 96 bits.
Another important register is INTA reg. PCI/MCU should set its value when RTR value is stable and contains the right Time Stamp.

PCI interface

As all of the TERs are wider than PCI bus (96 bits) and must be read and written in one time, the acces to them is done by PCI Temporary Register (PTR) which is 96 bits wide. TERs can be driven also by embeded Microcontroler (MCU). It depends on TSU CTRL register (see TSU CTRL reg description).

Write operation

is done in two steps. First store desired value into PTR register via PCI. Then store right command into PCI Control Register (PCR) and content of PTR register will be copied into one of TERs.

Read operation

is done in two steps. First store right command into PCI Control Register (PCR) and content of desired TERs register will be copied into PTR. Then you can read PTR value via PCI.

PCI Control Register (PCR)

When you store a new value into PCR, an r/w operation will be done with one of the TERs specified in PCR command. See PCI CTRL reg description.

MCU interface

PTM initialization should be done by embeded MCU instead of software. Data bus between MCU and FPGA is only 8 bits wide and TERs must be read/written in one time, so MCU Temporary Register (MTR - 96 bits wide) must be used.

Write operation

is done in two steps. First you must in sequence store desired value into MTR register. Then you can store MTR content into INCR or RTR register. All of those operations are driven by MCU port (see MCU port description).

Read operation

is done in two steps. First you must load content of desired TERs register into MTR. Then you can read MTR value via FPGA <-> MCU data bus. All of those operations are driven by MCU port (see MCU port description).