Author:

Viktor Pus

This component is interface for DDR SDRAM on Combo6X card. It consists of three parts. Lower part is responsible for memory initialization, proper timing and the whole data pipeline. Higher part decodes simple "Read" and "Write" commands to real SDRAM commands, i.e PRECHARGE, ACTIVE, READ and WRITE. SDRAM_LB_Conn connects localbus and any other unit to the rest of the driver. Pictures not supported anymore.
Designed structure of the driver

Subcomponents:

Low level DDR SDRAM driver
This component provides communication with DDR SDRAM. It is resposible for initialization, proper timing of commands, writing and reading of data at double data rate.

High level DDR SDRAM driver
This component decodes simple "Read" and "Write" commands to real SDRAM commands, i.e PRECHARGE, ACTIVE, READ and WRITE.

Localbus connection to DDR SDRAM driver
This component makes DDR SDRAM accessible for reading and writing from software and one another component. These requests from both inputs are sent to SDRAM driver, with different TAG input. If the request was Read, SDRAM driver returns the TAG back together with data, so that this component may decide where the data belongs to. There is special software operation Load Mode Register, which allows software to change parameters of SDRAM on the fly.

Fake RAM
This is synthesizable component that behaves similarly like sdram_ctrl_high + sdram_ctrl_low + DDR SDRAM.

SPD driver
This component access SPD EEPROM for writing and reading purposes.

Communication

Unit connected to SDRAM_CTRL may send read or write requests to the controller. When writing, the first data must be written at the same cycle. If the burst lenght is four or eight, then next data must be written immediately one after another.

Reading latency is at least 10 cycles (when requested row is allready open), but it can also be 13 (when no row is open) or even 15 cycles (when another row is open).

CACHE_TAG_IN signal assigns tag to every operation that is sent to sdram_ctrl. When the operation is read, the value of this tag is returned together with corresponding data at the CACHE_TAG_OUT port.

Low level

Communication with high level driver is done via synchronous FIFOs. This component generates its own clock signal in the DCM. When RESET goes low, initialization sequence is sent to SDRAM. After that, commands are processed, keeping the required delays between them. When reading, special input TAG_IN is returned back as TAG_OUT together with the data. This may be used for deciding where the READ command came from.

High level

Decoder translates simple Read and Write command to the real SDRAM commands. It stores information about which row in each bank of memory is open. According this information, and the desired read or write addres, it decides whether it is needed to precharge and open the row in the desired bank. There is a refresh counter, which is used to send periodial REFRESH commands to SDRAM.

SDRAM_LB_CONN

This component decides between requests from unit and localbus. Requests from both sources are marked with different Tag, so that read data are put to the correct output.