| Info | HW section | SW section | Addr space | Interface | Versions |
| Authors: | Jan Pazdera |
| Martin Mikusek | |
| Petr Mikusek | |
| Tomas Martinek |
Packet FIFO is divided into two parts: PFIFO_A and PFIFO_B. Due to this PFIFO can provide inter-design connection. It converts 16 bit input data into 32 bit data.
PFIFO_A is conected with four HFE interfaces and provides DRAM scheduler functions. It converts HFE data into new format PFIFO_B can work with and send them via four streams to PFIFO_B.
PFIFO_B recieves 4 data strems from PFIFO_A, which are stored into FIFO16TO32. It is also connected with Sorting Unit (SU), Dispatcher (DISP) and SFIFO. It use SU records to sort packets from four streams into one in previous order (as they were recieved from HFEs). It also separates control data from input streams, sorts them and stores into SFIFO. DISP can read sorted 32 bit packets from PFIFO or it can free them directly without reading.
Packet FIFO Architecture
Subcomponents:
PFIFO component
Packet FIFO (PFIFO) component consists of two parts (PFIFO_A and PFIFO_B) which are connected together. This connection can be used to perform inter-design connections. It provides HFE <-> DRAM scheduler protocol, converts 4 input 16b data streams (from HFE) into 1 output 32b data stream (to DISP). It preforms incoming packets sorting with cooperation of SU. It also separates control data from incoming stream and stores them into SFIFO.
Data Stream Format
Data stream format from PFIFO_A. It is propagated throught PFIFO_B into DISP.
For each 8 data bits - 1 control bit:
| Control bit | Data |
| 0 | Data |
| 1 | Command |
Table 1:
List of Commands:
| Idle |
| Terminate |
| SOP (Start of Packet) |
| SOC (Start of Control) |
Table 2:
Example of Data Stream
{SOP}{Data}{Terminate}{SOC}{Data}{Terminate}
Additional Rules for Data Stream Format
- "Terminate" command can occure in an arbitrary position of input data word. The rest (if any) of the data word has to be filled with "Idle" commands.
- Each command except "Terminate" and "Idle" has to occure in the first octet of data word. The rest (if any) of the data word has to be filled with "Idle" commands.
- Idle Command can't occure inside data word (for instance 32-bit data word with "Data-Data-Idle-Data" isn't allowed).
Example of 32-bit data stream:
| 3 | Idle | Data | Data | Idle | Idle | Idle | Data | Idle |
| 2 | Idle | Data | Data | Idle | Term | Idle | Data | Idle |
| 1 | Idle | Data | Data | Idle | Data | Idle | Data | Term |
| 0 | SOP | Data | Data | Idle | Data | SOC | Data | Data |
Table 3:
PFIFO_A Specification
Converts Input Data Streams from 4 HFEs to 4 Output Data Streams.
Input Data Stream
| 16 bits | HFE Control Word |
| 16 bits | Identification |
| 64 bits | Time Stamp |
| XX | Packet Data (until EOP) |
Table 4:
Output Data Stream
| 8 bits | Start of Packet Command {SOP} |
| XX | Packet Data |
| 8 bits | Terminate Command {Term} |
| 8 bits | Start of Control Command {SOC} |
| 16 bits | Identification |
| 64 bits | Time Stamp |
| 16 bits | Length |
| 8 bits | Terminate Command {Term} |
Table 5:
DRAM FSM
- handles HFE - DRAMSH protocol
- converts input data into the "Data Stream Format"
- provides packet's length computation (for statistics purposes)
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PFIFO_A DRAMSH FSM Architecture
PFIFO_B Specification
Converts four input 16b data streams from PFIFO_A into one 32b data stream to Dispatcher. It also propagates control data from input streams into SFIFO in right order (sorted by Sorting Unit).
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PFIFO_B Architecture
4x PFIFO_B_ONE
PFIFO_B contains four PFIFO_B_ONE components. Each of them is used to process one incoming data stream from PFIFO_A. It consists of those parts: FIFO16TO32, Command Decoder, RECV_FSM and TSL_FIFO. See their descriptions below.
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PFIFO_B_ONE Architecture
FIFO16TO32
This component stores incoming packets from HFE. DISP can read them or release them immidiatelly. It provides 16b->32b conversion.
- Received data
- a start of packet is always aligned to 32 bit border
- at the end of packet, the FIFO logic is responsible for alignment
- so FIFO have to recognize "Terminate command"
- Packet copying
- a whole packet will be sent to the output only if GET_PACKET request is asserted. It is needed for clean output pipeline at the end of packet transfer
- Whole packet releasing on FREE_LSTBLK request
- FIFO has small internal FIFO for start position of each packet
- On request, a FIFO modifies read counter with next start position
Command Decoder
Decodes commands in data stream incoming from PFIFO_A and distinguishes commands and data
Recv FSM
Copies Identification, TimeStamp and Length information into the TSL FIFO
TSL FIFO
It provides control data (ID(16), TS(64), Len(16)) storing. Then the control data are processed by TSL_FSM.
SU FIFO
Stores interface identification from Sorting Unit
TSL FSM
- forwards data from dedicated TSL FIFO to SFIFO (except ID)
- right TSL FIFO is dedicated via interface identification from SU FIFO
TSL_FSM performs:
- Take record from SU FIFO
- Read 6x16-bits words (TimeStamp and Length - ID is trashed) and forwards them into SFIFO
- Generate TS_WR and LEN_WR signals
