Authors:	Petr Mikusek
	Tomas Pecenka

Sampling unit (SAU) performs sampling of packets which are required to pass to the application. Sampling units contains 16 Sampling Cores (SC). Each Sampling Core can be configured to do deterministic, length deterministic and probabilistic sampling. The packet could be processed simultaneously in more than one SAU core. Sampling unit has two inputs: (1) LUP record created by Look up processor (LUP) and (2) length of actual packet. Output from SAU is 16bit sample vector. Each bit of sample vector corresponds to result of one Sampling Core. Pictures not supported anymore.
Block structure of the Sampling Unit component

Sampling unit blocks

SAU consists of several identical SAU cores and control logic. Control logic generates control signals for SAU cores, it communicates with Sync FIFO and can be used to enable/disable and configure parameters of SAU cores from SW via the Local bus.

It's guaranteed that LUP generates max. four LUP records per 16 clock periods. Thus FIFO is between LUP and SAU and we have four clock periods for processing one packet.

Sampling unit core

Each sampling core can be be configured to do:

• deterministic sampling - each n-th packet is passed through
• length deterministic sampling - packet containing each n-th byte is passed through
• probabilistic sampling - the packet is passed through the unit with the probability p where treshold is computed as n = (2³²-1) * (1-p)

Basic approach for sampling is comparing certain value against treshold value. If certain value is equal or greater than value of treshold then actual packet is sampled.

This value is for determinstic sampling mode computed as a sum of count of packets. Similarly for length deterministic mode it is computed as sum of packet lengths. Finally for probabilistic sampling mode is used value from pseudo-random number generator.

Special configuration of SAU is the case of deterministic sampling with n = 1. This case represents the situation when all packets are sampled.

Linear feedback shift register

Linear feedback shift register (LFSR) is used to generate pseudo-random numbers. This block is used as the main part for probabilistic sampling. Pseudo-random number sequence can be determined by setting the seed (initial) value.