Authors:	Stepan Friedl
	Tomas Martinek

The transmit buffer (TXBUFF) component provides an interface for SW driven packet transmit operation and a simple interface for HW controlled packet transmission. The packet output is done by the standard GMII interface.

TX Buffer's building blocks

The TXBUFF component consists of two independent sets of BlockRAM buffers (the first one for SW operation, the second one for HW transmit), an arbitration logic, L2 packet encapsulation (SDF, preamble and CRC) and a logic driving the GMII interface.

Transmit operation driven by SW

A set of data buffers and control registers is accessible (mapped to the memory) via the local bus (ADC ports on component's interface) to the software. The transmit operation consists of writing the packet data to a data buffer, specifying data length and starting the operation. For more information see the SW and Address space sections.

HW driven transmit operation

A simple protocol is defined for passing the packet data from an another HW component: The rising edge of the TXDV_IN signal indicates start of packet data, the falling edge terminates the data. The TXDV_IN must not fall during a single data frame, otherwise the frame will be divided into two packets.

HW/SW transmit arbitration

A fair arbitration system is implemented, the transmit operation alternates between HW and SW TX buffers.