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Main page -> VHDL
Interconnection System
InfoHW sectionSW sectionAddr space
Author:   Petr Kobiersky

Overview of Interconnection system. See HW section ( link) for list of available components.

Features:

  • Full duplex internal bus with packet oriented communication
  • Tree architecture based on Root, Endpoints and Switches
  • Link characteristics: Upstream and Downstream port, 128/64 data width at 125 MHz
  • Programmable busmaster controller based on embedded PowerPC processor

    • Todo:

  • Hardware testing

    • Bugs:

  • Not known bugs
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