Program

Slides from the presentation: PPT, PDF, HTML.

• Introduction to the operation of an Internet Router
• • Control plane
  • • Routing protocols
    • Routing table
    • Management interfaces
  • Datapath
  • • Longest Prefix Match (LPM)
    • Classless Interdomain Routing (CIDR)
    • Header processing
    • Packet buffering
• The NetFPGA Router
• • Hardware
  • • Gigabit Ethernet interfaces
    • Field Programmable Gate Array (FPGA) Logic
    • Random Access Memory (RAM)
  • Software
  • • Kernel-space driver
    • User-space applications
    • PCI host interface
  • System configuration
• Integrated Circuit Design
• • Technologies
  • • Look-Up Tables (LUTs)
    • Configurable Logic Blocks (CLBs)
    • Field Programmable Gate Arrays (FPGAs)
  • Verilog Hardware Description Langauge (HDL)
  • • Registers, integers, arrays
    • Multiplexers
    • Synchronous storage elements
    • Finite State Machines (FSMs)
  • Hardware Debug
  • • Waveform monitor
    • In-circuit logic emulation
• NetFPGA System Components
• • Synthesis of tutorial router
  • Java-based Graphical User Interface (GUI)
  • • Configuration
    • Statistics
  • Router architecture
  • • Pipeline
    • Queues
• Buffer Size Experiment
• • Experiment with TCP/IP flows
  • • Rule-of-thumb for the buffer size
    • Round-trip propagation delay
    • Capacity of bottleneck link
    • Number of active flows
  • Lower delay with smaller queues
• Enhanced Router
• • Additional hardware
  • • Event capture module
    • Rate limiter
    • Delay module
  • Experiments
  • • Netperf
    • HD video transport
  • Life of packet through the system
  • • Description of blocks
    • Waveforms from logic analyzer