Cesnet Liberouter
  • Projects
  • Liberouter
  • Scampi
  • FlowMon
  • NIC
  • NIFIC
  • IDS
  • NetCOPE
  • VHDL design
  • System software
  • Testing
  • Formal verification
  • Netopeer
  • Documents
  • Our hardware
  • Card Availability
  • Our partners
Main page -> Documents -> Policy -> VHDL source file policy
VHDL source file policy

File format

  • At the begining of the source file, there has to be file header and licence. Here is an example.
  • Maximal length of line is 80 characters.
  • All tabs are expanded to 3 spaces.
  • Every comment has to be in english.
  • Every process should be commented (register, conter, etc.)

Signal names

  • Signal names in entity inrface are all upper case.
  • Signals that are not defined in entity interface has to be all lower case.
  • Words are separated by underline character ("_").
  • Use short names ("clk").
Main Page About Liberouter Team Mailing list SVN Contacts